INTEL 

Intel 82541ER Gigabit Ethernet Controller


Mfg Part Number:  GD82541ER  
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Price: $194.89 + Free Shipping
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In Stock: 1
Last Updated: Apr 18, 2024
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PCI Bus Features
PCI revision 2.3, 32-bit, 33/66MHz Application flexibility for embedded board designs
CLKRUN# Signal PCI clock suspension for low-power designs
Gigabit MAC Features
64KB configurable RX and TX packet FIFO
No external FIFO memory requirements
FIFO size tunable to the application
IEEE 802.3x compliant flow control support Reduced frame loss due to receive FIFO overrun
Programmable host memory receive buffers (256B to 16KB) Efficient usage of system resources
Low-latency transmit and receive queues Network packets handled without waiting or buffer overflow
Gigabit PHY Features
IEEE 802.3ab Auto-Negotiation Automatic link configuration including speed, duplex, and flow control
State-of-the-art DSP/analog architecture
Implements digital adaptive equalization, echo, cross-talk and baseline wander cancellation
Robust 1000Mbps performance in noisy environments
PHY detects polarity Easier network installation and maintenance
PHY supports 2 pair and 3 pair cable downshift Controller adapts to sub-standard cable plant
Host Offloading Features
Transmit TCP segmentation, and IP, TCP, and UDP checksum off-loading
Increased throughput and lower CPU utilization
Compatible with large send offload on RX and TX
Interrupt moderation controls Reduces number of interrupts generated by RX and TX operations, resulting in lower CPU utilization
Jumbo frame support up to 16KB High throughput for large data transfers on networks supporting jumbo frames
Power Management Features
Compliance with PCI Power Management v1.1/ACPI v2.0 PCI power management capabilities for embedded applications
Automatic link speed switching from 1000Mbps down to 10 or 100Mbps in standby
Supports power-down states without software assistance
Low power in standby states
Smart Power Down mode when no signal is detected on the wire Enables very low power consumption
Additional Features
Four programmable LED outputs Customizable indications for link speed, activity, duplex, collisions, and port ID on each port
On-chip power regulator control circuitry Simplified low-cost power supply design
Internal PLL for clock generation using a 25MHz crystal or a 25MHz oscillator Lower component count and cost
BIOS LAN Disable Pin Enables low-power LAN disable via BIOS
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